The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple dielectric and conductor deposition processes followed by the masking and etching of the deposited layers. Some of these steps relate to metallization, which generally refers to the materials, methods, and processes of wiring together or interconnecting the component parts of an integrated circuit located on or overlying the surface of the wafer. Typically, the wiring of an integrated circuit involves etching features, such as “trenches” and “vias,” in a planar dielectric (insulator) layer and filling the features with a conductive material, typically a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to the ease with which aluminum could be applied and patterned on the wafer. In addition, aluminum metallization does not suffer from the leakage and adhesion problems experienced with the use of gold. Other metallization materials have included such materials as Ni, Ta, Ti, W, Ag, Al(Cu), TaN, TiN, CoWP, NiP and CoP, alone or in various combinations.
Recently, techniques have been developed which utilize copper to form conductive contacts and interconnects because copper is less susceptible to electromigration and exhibits a lower resistivity than aluminum. Since copper does not readily form volatile compounds, the plasma etching of copper is difficult. Hence, conductive contacts and interconnects often are formed using a damascene process. In accordance with the damascene process, the copper conductive contacts and interconnects are usually formed by etching features such as vias and/or trenches within a blanket insulating material. The vias and/or trenches may be formed wholly within one insulating material layer or may be etched to expose other insulating material layers or metallic layers. A barrier layer, which serves to prevent catastrophic contamination caused by copper diffusing through the interlayer dielectrics, typically may be deposited onto the surface of the insulating material and within the vias and/or trenches. Because it is often difficult to form a copper metallization layer directly overlying the barrier layer using electroplating, a seed layer of copper may be deposited onto the barrier layer. Then, a copper metallization layer may be electrodeposited onto the seed layer to fill the vias and/or trenches. The excess copper metallization layer, the copper seed layer, and the barrier layer overlying the insulating material outside the vias and/or trenches then may be removed, for example, by a process of chemical mechanical planarization or chemical mechanical polishing, each of which will hereafter be referred to as chemical mechanical planarization or CMP.
Tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN) currently are used as barrier layers in copper interconnects. However, it is difficult to electroplate copper directly onto thin barrier layers of Ta, TaN, and TiN because these barrier materials are highly resistive. Further, Ta, TaN, and TiN have a tendency to form an oxide film that is difficult to remove. This oxide film may prevent sufficient adhesion of the copper to the work piece. Accordingly, it is typically necessary to deposit a seed layer overlying the barrier layer to facilitate the deposition of copper. However, poor sidewall coverage and large overhang of the copper seed layer in the features may cause the copper electrofill to close off and leave voids in the features. As integrated circuits continue to scale to 90 nm, 65 nm, 45 nm and smaller technology nodes, it may become difficult to further decrease the dimensions of the barrier layer and seed layer in higher-aspect ratio features. This decrease is needed to allow for void-free filling with copper.
Barrier layers formed of ruthenium may present a desirable alternative to Ta, TaN, and TiN barriers. Ruthenium is an air-stable transition metal with a high melting point and is at least ten times more electrically conductive than tantalum. In addition, ruthenium generally shows negligible solid solubility with copper, thereby minimizing the adverse increase in the resistivity of copper from dissolution of dopants in the copper. Further, copper demonstrates suitable adhesion to ruthenium when directly deposited thereon. However, ruthenium demonstrates a tendency to form a ruthenium oxide layer overlying the ruthenium layer when exposed to ambient conditions. This ruthenium oxide layer may interfere with the deposition of copper directly onto the ruthenium layer.
Accordingly, it is desirable to provide a method for the electrochemical deposition of copper directly on a barrier layer of a semiconductor substrate. In addition, it is desirable to provide a method for the deposition of copper on a semiconductor work piece wherein the method eliminates the need for the deposition of a seed layer overlying the barrier layer. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.